[Comp-neuro] Transistor analogs of emergent iono-neuronal dynamics

Chi-Sang Poon cpoon at MIT.EDU
Mon Apr 21 00:59:50 CEST 2008

*Apologies for multiple postings*


Guy Rachmuth and Chi-Sang Poon. Transistor analogs of emergent iono-neuronal
dynamics. HFSP Journal (in press)


Epub 2008 April 18: <http://scitation.aip.org/dbt/dbt.jsp?KEY=HFSPJX

Reprint request: cpoon at mit.edu



Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise
compact, low-power, and high-speed emulations of iono-neuronal dynamics
orders-of-magnitude faster than digital simulation. However, their
inherently limited input voltage dynamic range vs power consumption and
silicon die area tradeoffs makes them highly sensitive to transistor
mismatch due to fabrication inaccuracy, device noise, and other
nonidealities. This limitation precludes robust analog
very-large-scale-integration (aVLSI) circuits implementation of emergent
iono-neuronal dynamics computations beyond simple spiking with limited ion
channel dynamics. Here we present versatile neuromorphic analog
building-block circuits that afford near-maximum voltage dynamic range
operating within the low-power MOS transistor weak-inversion regime which is
ideal for aVLSI implementation or implantable biomimetic device
applications. The fabricated microchip allowed robust realization of dynamic
iono-neuronal computations such as coincidence detection of presynaptic
spikes or pre- and postsynaptic activities. As a critical performance
benchmark, the high-speed and highly interactive iono-neuronal simulation
capability on-chip enabled our prompt discovery of a minimal model of
chaotic pacemaker bursting, an emergent iono-neuronal behavior of
fundamental biological significance which has hitherto defied experimental
testing or computational exploration via conventional digital or analog
simulations. These compact and power-efficient transistor analogs of
emergent iono-neuronal dynamics open new avenues for next-generation
neuromorphic, neuroprosthetic, and brain-machine interface applications.
C2008 HFSP Publishing

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